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description the digital interface ic, hcpl- 0872 converts the single-bit data stream from the isolated modulator (such as hcpl- 7860/786j/7560) into fifteen- bit output words and provides a serial output interface that is compatible with spi ? , qspi ? , and microwire ? protocols, allowing direct connection to a microcontroller. the digital interface ic, HCPL-0872 is available a 300-mil wide so-16 surface-mount package. features ? ? ? ? ? interface between hcpl-7860/ 786j/7560 and mcu/dsp ? ? ? ? ? 5 conversion modes for resolution/speed trade-off ? ? ? ? ? 3 pre-trigger modes ? ? ? ? ? offset calibration ? ? ? ? ? fast 3 s over-range detection ? ? ? ? ? adjustable threshold detection ? ? ? ? ? serial i/o (spi ? , qspi ? and microwire compatible) ? ? ? ? ? offset calibration ? ? ? ? ? -40c to +85c operating temperature range applications ? ? ? ? ? motor phase and rail current sensing ? ? ? ? ? data acquisition systems ? ? ? ? ? industrial process control ? ? ? ? ? inverter current sensing ? ? ? ? ? general purpose current sensing and monitoring agilent HCPL-0872 digital interface ic data sheet features of the digital interface ic include five different conversion modes, three different pre-trigger modes, offset calibration, fast over-range detection, and adjustable threshold detection. programmable features are configured via the serial configuration port. a second multiplexed input is available to allow measurements with a second isolated modulator without additional hardware. spi and qspi are trademarks of motorola corp. microwire is a trademark of national semiconductor inc. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. a 0.1 f bypass capacitor must be connected between pins v dd and ground HCPL-0872 mcu or dsp 1 2 3 4 5 8 6 7 14 13 12 16 15 9 11 10 config inter- face con version inter- face ch1 ch2 thres hold detect & reset cclk clat cdat mclk1 mdat1 mclk2 mdat2 gnd thr1 ovr1 reset sdat cs v dd chan sclk v dd1 v in+ v in- gnd1 v dd2 mclk mdat gnd2 input current hcpl-7860 hcpl-786j hcpl-7560 v dd1 v in+ v in- gnd1 v dd2 mclk mdat gnd2 - - - - - - input current
2 HCPL-0872 digital interface ic because the two inputs are multiplexed, only one conversion at a time can be made and not all features are pin description, digital interface ic symbol description cclk clock input for the serial configuration interface (sci). serial configuration data is clocked in on the rising edge of cclk. clat latch input for the serial configuration interface (sci). the last 8 data bits clocked in on cdat by cclk are latched into the appropriate configuration register on the rising edge of clat. cdat data input for the serial configuration interface (sci). serial configuration data is clocked in msb first. mclk1 channel 1 isolated modulator clock input. input data on mdat1 is clocked in on the rising edge of mclk1. mdat1 channel 1 isolated modulator data input. mclk2 channel 2 isolated modulator clock input. input data on mdat2 is clocked in on the rising edge of mclk2. mdat2 channel 2 isolated modulator data input. gnd digital ground. vdd supply voltage (4.5 v to 5.5 v). chan channel select input. the input level on chan determines which channel of data is used during the next conversion cycle. an input low selects channel 1, a high selects channel 2. sclk serial clock input. serial data is clocked out of sdat on the falling edge of sclk. sdat serial data output. sdat changes from high impedance to a logic low output at the start of a conversion cycle. sdat then goes high to indicate that data is ready to be clocked out. sdat returns to a high- impedance state after all data has been clocked out and cs has been brought high. sdat goes high immediately after reset is released. cs conversion start input. conversion begins on the falling edge of cs. cs should remain low during the entire conversion cycle and then be brought high to conclude the cycle. thr1 continuous, programmable-threshold detection for channel 1 input data. a high level output on thr1 indicates that the magnitude of the channel 1 input signal is beyond a user programmable threshold level between 160 mv and 310 mv. this signal continuously monitors channel 1 independent of the channel select (chan) signal. ovr1 high speed continuous over-range detection for channel 1 input data. a high level output on ovr1 indicates that the magnitude of the channel 1 input is beyond full-scale. this signal continuously monitors channel 1 independent of the chan signal. reset master reset input. a logic high input for at least 100 ns asynchronously resets all configuration registers to their default values and zeroes the offset calibration registers. 5 6 12 11 mdat1 mclk2 cs thr1 con- version inter- face config. inter- face 7 10 mdat2 ovr1 8 9 gnd reset 1 2 16 15 cclk clat v dd chan 3 14 cdat sclk 4 13 mclk1 sdat ch1 ch2 thres- hold detect & reset available for the second channel. the available features for both channels are shown in the table below feature channel 1 channel 2 conversion mode ?? offset calibration ?? pre-trigger mode ? over-range detection ? adjustable threshold detection ?
3 package outline drawings standard 16-pin so package ordering information specify part number followed by option number (if desired). example: option data sheets available. contact agilent sales representative or authorized distributor. 9 10.00-10.65 (0.394-0.419) (tip to tip) 2.386-2.586 (0.094-0.1018) 1.27 bsc (0.050 bsc) a 0872 yyww 2.286 (0.090) 1.90 (0.075) 1.90 (0.075) 7.544 0.05 (0.297 0.002) 0.33 x 45 ? (0.013 x 45 ? ) pin no. 1 identifier ? 1.27 (0.050) x 0.075 (0.003) depth shiny surface 1.27 (0.050) 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 10.21 0.10 (0.402 0.002) 0.33-0.51 (0.013-0.020) 0.01 (0.004) 0.10-0.30 (0.004-0.0118) 1.016 0.025 (0.040 0.001) r 0.18 (r 0.007) all corners and edges seating plane th xx top view bottom view side view end view a 1.016 ref. (0.040) 0.40 - 1.27 (0.016 - 0.050) 0 ? - 8 ? 7 ? detail a ? 1.27 (0.050) x 0.075 (0.003) depth (2x) ejector pin shiny surface 0.23-0.32 (0.0091-0.0125) parting line dimensions in millimeters (inches). tolerances (unless otherwise specified): xx.xx = 0.010 xx.xxx = 0.002 1.27 (0.050) HCPL-0872-xxxx no option = standard 16-pin so package, 47 units per tube. 500 = tape and reel packaging option, 1000 units per reel. xxxe = lead-free option
4 solder reflow temperature profile recommended pb-free ir profile 0 time (seconds) temperature (?c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160?c 140?c 150?c peak temp. 245?c peak temp. 240?c peak temp. 230?c soldering time 200?c preheating time 150?c, 90 + 30 sec. 2.5?c 0.5?c/sec. 3?c + 1?c/-0.5?c tight typical loose room temperature preheating rate 3?c + 1?c/-0.5?c/sec. reflow heating rate 2.5?c 0.5?c/sec. 217 ? c ramp-down 6 ? c/sec. max. ramp-up 3 ? c/sec. max. 150 - 200 ? c 260 +0/-5 ? c t 25 ? c to peak 60 to 150 sec. 20-40 sec. time within 5 ? c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time (seconds) temperature ( ? c) notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 ? c, t smin = 150 ? c
5 electrical specifications (dc) unless otherwise noted, all typical specifications are at t a = 25c and v dd = 5 v, and all minimum and maximum specifications apply over the following ranges: t a = -40c to +85c and v dd = 4.5 to 5.5 v. absolute maximum ratings notes: 1. agilent recommends the use of non-chlorinated solder fluxes. notes 1. agilent technologies recommends the use of non-chlorinated solder fluxes. recommended operating conditions parameter symbol min. max. units ambient operating temperature t a -40 85 c supply voltage v dd 4.5 5.5 v input voltage all inputs 0 v dd v parameter symbol min. typ. max. units test conditions fig. supply current i dd 35maf clk = 10 mhz dc input current i in 0.001 10 a input logic low voltage v il 0.8 v input logic high voltage v ih 3.6 v output logic low voltage v ol 0.15 0.4 v i out = 4 ma output logic high voltage v oh 4.3 5.0 v i out = -400 a clock frequency (cclk, mclk and sclk) f clk 20 mhz clock period (cclk, mclk and sclk) t per 50 ns 2, 3 clock high level pulse width (cclk, mclk and sclk) t pwh 20 ns 2, 3 clock low level pulse width (cclk, mclk and sclk) t pwl 20 ns 2, 3 setup time from dat to rising edge of clk (cdat, cclk, mdat and mclk) t suclk 10 ns 2 dat hold time after rising edge of clk (cdat, cclk, mdat and mclk) t hdclk 10 ns 2 setup time from falling edge of clat to first rising edge of cclk t sucl1 20 ns 2 setup time from last rising edge of cclk to rising edge of clat t sucl2 20 ns 2 delay time from falling edge of sclk to sdat t dsdat 15 ns 3 setup time from data ready to first falling edge of sclk t sus 200 ns 3 setup time from chan to falling edge of cs t suchs 20 ns reset high level pulse width t pwr 100 ns parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 85 c supply voltage v dd 05.5v input voltage all inputs -0.5 v dd + 0.5 v output voltage all outputs -0.5 v dd + 0.5 v lead solder temperature 260c for 10 sec., 1.6 mm below seating plane 1 solder reflow temperature profile see reflow thermal profile
6 product description the digital interface ic, hcpl- 0872 converts the single-bit data stream from the isolated modulator (such as hcpl- 7860/786j/7560) into fifteen- bit output words and provides a serial output interface that is compatible with spi ? , qspi ? , and microwire ? protocols, allowing direct connection to a microcontroller. a second multiplexed input is available to allow measurements with a second isolated modulator without additional hardware. the digital interface ic, hcpl- 0872 can used together with isolated modulator, hcpl- 7860/786j/7560 to form an isolated programmable two- chip analog-to-digital converter. the primary functions of the HCPL-0872 digital interface ic are to derive a multi-bit output signal by averaging the single- bit modulator data, as well as to provide a direct microcontroller interface. the effective resolution of the multi-bit output signal is a function of the length of time (measured in modulator clock cycles) over which the average is taken; averaging over longer periods of time results in higher resolution. the digital interface ic can be configured for five conversion modes, which have different combinations of speed and resolution to achieve the desired level of performance. other functions of the hcpl- 0872 digital interface ic include a phase locked loop based pre-trigger circuit that can either give more precise control of the effective sampling time or reduce conversion time to less than 1 s, a fast over-range detection circuit that rapidly indicates when the magnitude of the input signal is beyond full- scale, an adjustable threshold detection circuit that indicates when the magnitude of the input signal is above a user adjustable threshold level, an offset calibration circuit, and a second multiplexed input that allows a second isolated modulator to be used with a single digital interface ic. applications information digital current sensing as shown in figure 1, using the isolated 2-chip a/d converter to sense current can be as simple as connecting a current-sensing resistor, or shunt, to the input and reading output data through the 3-wire serial output interface. by choosing the appropriate shunt resistance, any range of current can be monitored, from less than 1 a to more than 100 a. even better performance can be achieved by fully utilizing the more advanced features of the isolated a/d converter, such as the pre-trigger circuit, which can reduce conversion time to less than 1 s, the fast over-range detector for quickly detecting short circuits, different conversion modes giving various resolution/speed trade-offs, offset calibration mode to eliminate initial offset from measurements, and an adjustable threshold detector for detecting non-short circuit overload conditions. figure 1. typical application circuit. r shunt 0.02 input current v dd1 isolated + 5 v v in+ v in- gnd1 v dd2 mclk mdat gnd2 c1 0.1 f + cdat sclk cclk v dd clat chan mclk1 sdat mdat1 cs mclk2 thr1 mdat2 ovr1 gnd reset non-isolated + 5 v c3 10 f + hcpl-7860 hcpl-786j hcpl-7560 3-wire serial interface c2 0.1 f HCPL-0872
7 digital interface timing power up/reset at power up, the digital interface ic should be reset either manually, by bringing the reset pin (pin 9) high for at least 100 ns, or automatically by connecting a 10 f capacitor between the reset pin and v dd (pin 16). the reset pin operates asynchronously and places the ic in its default configuration, as specified in the digital interface configuration section. cycle. if the external circuit uses the positive edges of sclk to clock in the data, then a total of sixteen bits is clocked in, the first bit is always high (indicating that data is ready) followed by 15 data bits. if fewer than 16 cycles of sclk are input before cs is brought high, the conversion cycle will terminate and sdat will go to the high- impedance state after a few cycles of the isolated modulators clock. the amount of time between the falling edge of cs and the rising edge of sdat depends on which conversion and pre- trigger modes are selected; it can be as low as 0.7 s when using pre-trigger mode 2, as explained in the digital interface configuration section. figure 2. conversion timing. conversion timing figure 2 illustrates the timing for one complete conversion cycle. a conversion cycle is initiated on the falling edge of the convert start signal (cs); cs should be held low during the entire conversion cycle. when cs is brought low, the serial output data line (sdat) changes from a high- impedance to the low state, indicating that the converter is busy. a rising edge on sdat indicates that data is ready to be clocked out. the output data is clocked out on the negative edges of the serial clock pulses (sclk), msb first. a total of 16 pulses is needed to clock out all of the data. after the last clock pulse, cs should be brought high again, causing sdat to return to a high-impedance state, completing the conversion sclk sdat chan t suchs t dsdat t c t sus b14 b13 b12 b11 b10 b1 b0 123456 t per t pwl 15 16 t pwh cs
8 serial configuration timing the HCPL-0872 digital interface ic is programmed using the serial configuration interface (sci), which consists of the clock (cclk), data (cdat), and enable/latch (clat) signals. figure 3 illustrates the timing for the serial configuration interface. to send a byte of configuration data to the HCPL-0872, first bring clat low. then clock in the eight bits of the configuration byte (msb first) using cdat and the rising edge of cclk. after the last bit has been clocked channel select timing the channel select signal (chan) determines which input channel will be used for the next conversion cycle. a logic low level selects channel one, a high level selects channel 2. chan should not be changed during a conversion cycle. the state of the chan signal has no effect on the behavior of either the over-range detection circuit (ovr1) or the adjustable threshold detection circuit (thr1). both ovr1 and thr1 continuously monitor channel 1 independent of the chan signal. chan also does not affect the behavior of the pre- trigger circuit, which is tied to the conversion timing of channel 1, as explained in the digital interface configuration section. in, bringing clat high again will latch the data into the appropriate configuration register inside the interface ic. if more than eight bits are clocked in before clat is brought high, only the last eight bits will be used. refer to the digital interface configuration section to determine appropriate configuration data. if the default configuration of the digital interface ic is acceptable, then cclk, cdin and clat may be connected to either v dd or gnd. figure 3. serial configuration interface timing. cclk cdat clat t suclk t hdclk t sucl1 t sucl2 t pwh t pwl t per b7 b6 b5 b4 b3 b2 b1 b0
9 digital interface configuration configuration registers the digital interface ic contains four 6-bit configuration registers that control its behavior. the two lsbs of any byte clocked into the serial configuration port (cdat, cclk, clat) are used as address bits to determine which register the data will be loaded into. registers 0 and 1 (with address bits 00 and 01) specify the conversion and offset calibration modes of channels 1 and 2, register 2 (address bits 10) specifies the table 1. register configuration. table 2. conversion mode configuration. notes: bold italic type indicates default values. conversion mode configuration data bits bit 7bit 6bit 5bit 4 1lowhighlowhigh 2lowlowhighhigh 3 highhighhighlow 4 high high low low 5highlowhighlow conversion mode the conversion mode determines the speed/ resolution trade-off for the isolated a/d converter. the four msbs of registers 0 and 1 determine the conversion mode for the appropriate channel. the bit settings for choosing a particular conversion mode are shown in table 2 below. combinations of data bits not specified in table 2 below are not recommended. notes: bold italic type indicates default values. reserved bits should be set low. configuration data bits address bits register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 channel 1 conversion mode channel 1 offset cal reserved high high low low low low low low 1 channel 2 conversion mode channel 2 offset cal reserved high high low low low low low high 2 threshold detection time threshold level high low low low low low high low 3 pre-trigger mode reserved low low low low low low high high behavior of the adjustable threshold circuit, and register 3 (address bits 11) specifies which pre-trigger mode to use for channel 1. these registers are illustrated in table 1 below, with default values indicated in bold italic type. note that there are several reserved bits, which should always be set low and that the configuration registers should not be changed during a conversion cycle.
10 figure 4. pre-trigger modes 0, 1, and 2. pre-trigger mode the pre-trigger mode refers to the operation of a pll-based circuit that affects the sampling behavior and conversion time of the a/d converter when channel 1 is selected. the pll pre-trigger circuit has two modes of operation; the first mode allows more precise control of the time at which the analog input voltage is effectively sampled, while the second mode essentially eliminates the time between when the external convert start command is given and when output data is available (reducing it to less than 1 s). a brief description of how the a/d converter works with the pre-trigger circuit disabled will help explain how the pre- trigger circuit affects operation when it is enabled. with the pre-trigger circuit is disabled (pre-trigger mode 0), figure 4 illustrates the relationship between the convert start command, the weighting function used to average the modulator data, and the data ready signal. the weighted averaging of the modulator data begins immediately following the convert start command. the weighting function increases for half of the conversion cycle and then decreases back to zero, at which time the data ready signal is given, completing the conversion cycle. the analog signal is effectively sampled at the peak of the weighting function, half- way through the conversion cycle. this is the default mode. if the convert start signal is periodic (i.e., at a fixed frequency) and the pll pre- trigger circuit is enabled (pre- trigger modes 1 or 2), either the peak of the weighting function or the end of the conversion cycle can be aligned to the external convert start command, as shown in figure 4. the digital interface ic can therefore synchronize the conversion cycle so that either the beginning, the middle, or the end of the conversion is aligned with the external convert start command, depending on whether pre-trigger mode 0, 1, or 2 is selected, respectively. the only requirement is that the convert start signal for channel 1 be periodic. if the signal is not periodic and pre- trigger mode 1 or 2 is selected, then the pre-trigger circuit will not function properly. weighting function convert start - cs data ready - sdat a) pre-trigger mode 0 b) pre-trigger mode 1 c) pre-trigger mode 2 an important distinction should be made concerning the difference between conversion time and signal delay. as can be seen in figure 4, the amount of time from the peak of the weighting function (when the input signal is being sampled) to when output data is ready is the same for all three modes. this is the actual delay of the analog signal through the a/d converter and is independent of the conversion time, which is simply the time between the convert start signal and the data ready signal. because signal delay is the true measure of how much phase shift the a/ d converter adds to the signal, it should be used when making calculations of phase margin and loop stability in feedback systems. there are different reasons for using each of the pre-trigger modes. if the signal is not periodic, then the pre-trigger circuit should be disabled by selecting pre-trigger mode 0. if the most time-accurate sampling of the input signal is desired, then mode 1 should be selected. if the shortest possible conversion time is desired, then mode 2 should be selected. the pre-trigger circuit functions only with channel 1; the circuit ignores any convert start signals while channel 2 is selected with the chan input. this allows conversions on channel 2 to be performed between conversions on channel 1 without affecting the operation of the pre-trigger circuit. as long as the convert start signals are periodic while channel 1 is selected, then the pre-trigger circuit will function properly. the three different pre-trigger modes are selected using bits 6 and 7 of register 3, as shown in table 3 below.
11 table 3. pre-trigger mode configuration. notes: bold italic type indicates default values. pre-trigger mode configuration data bits bit 7 bit 6 0lowlow 1lowhigh 2highdon't care offset calibration the offset calibration circuit can be used to separately calibrate the offsets of both channels 1 and 2. the offset calibration circuit contains a separate offset register for each channel. after an offset calibration sequence, the offset registers will contain a value equal to the measured offset, which will then be subtracted from all subsequent conversions. a hardware reset (bringing the reset pin high for at least 100 ns) is required to reset the offset calibration registers to zero. the following sequence is recommended for performing an offset calibration: 1. select the appropriate channel using the chan pin (low = channel 1, high = channel 2). 2. force zero volts at the input of the selected isolated modulator. 3. send a configuration data byte to the appropriate register for the selected channel (register 0 for channel 1, register 1 for channel 2). bit 3 of the configuration byte should be set high to enable offset calibration mode and bits 4 through 7 should be set to select conversion mode 1 to achieve the highest resolution measurement of the offset. 4. perform one complete conversion cycle by bringing cs low until sdat goes high, indicating completion of the conversion cycle. because bit 3 of the configuration has been set high, the uncalibrated output data from the conversion will be stored in the appropriate offset calibration register and will be subtracted from all subsequent conversions on that channel. if multiple conversion cycles are performed while the offset calibration mode is enabled, the uncalibrated data from the last conversion cycle will be stored in the offset calibration register. 5. send another configuration byte to the appropriate register for the selected channel, setting bit 3 low to disable calibration mode and setting bits 4 through 7 to select the desired conversion mode for subsequent conversions on that channel. to calibrate both channels, perform the above sequence for each channel. the offset calibration sequence can be performed as often as needed. table 4 below summarizes how to turn the offset calibration mode on or off using bit 3 of configuration registers 0 and 1. table 4. offset calibration configuration. notes: bold italic type indicates default values. offset calibration mode configuration data bits bit 3 off low on high over-range detection the over-range detection circuit allows fast detection of when the magnitude of the input signal on channel 1 is near or beyond full-scale, causing the ovr1 output to go high. this circuit can be very useful in current-sensing applications for quickly detecting when a short-circuit occurs. the over-range detection circuit works by detecting when the modulator output data has not changed state for at least 25 clock cycles in a row, indicating that the input signal is near or beyond full-scale, positive or negative. typical response time to over-range signals is less than 3 s. the over-range circuit actually begins to indicate an over- range condition when the magnitude of the input signal exceeds approximately 250 mv; it starts to generate periodic short pulses on ovr1, which get longer and more frequent as the input signal approaches full scale. the ovr1 output stays high continuously when the input is beyond full-scale. the over-range detection circuit continuously monitors channel 1 independent of which channel is selected with the chan signal. this allows continuous monitoring of channel 1 for faults while converting an input signal on channel 2.
www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. data subject to change. copyright ? 2005 agilent technologies, inc. february 2, 2005 obsoletes 5989-1423en 5989-2165en adjustable threshold detection the adjustable threshold detector causes the thr1 output to go high when the magnitude of the input signal on channel 1 exceeds a user- defined threshold level. the threshold level can be set to one of 16 different values between approximately 160 mv and 310 mv. the adjustable threshold detector uses a smaller version of the main conversion circuit in combination with a digital comparator to detect when the magnitude of the input signal on channel 1 is beyond the defined threshold level. as with the main conversion circuit, there is a trade-off between speed and resolution with the threshold detector; selecting faster detection times exhibit more noise as the signal passes through the threshold, while slower detection times offer lower noise. both the detection time and threshold level are programmable using bits 2 through 7 of configuration register 2, as shown in tables 5 and 6 below. as with the over-range detector, the adjustable threshold detector continuously monitors channel 1 independent of which channel is selected with the chan signal. this allows continuous monitoring of channel 1 for faults while converting channel 2. table 6. threshold level configuration. table 5. threshold detection configuration. notes: bold italic type indicates default values. notes: bold italic type indicates default values. threshold detection time configuration data bits bit 7 bit 6 2 - 6 s low low 3 - 10 s low high 5 - 20 s high low 10 - 35 s high high threshold level configuration data bits bit 5 bit 4 bit 3 bit 2 160 mv lowlowlowlow 170 mv low low low high 180 mv high low 190 mv high 200 mv high low low 210 mv high 220 mv high low 230 mv high 240 mv high low low low 250 mv high 260 mv high low 270 mv high 280 mv high low low 290 mv high 300 mv high low 310 mv high

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